RISC-V Processor Technology at the Core of IQonIC Works Silicon

IQonIC Works designs and delivers production-ready microcontroller and application-specific IC products built on proven RISC-V processor technology. Our RISC-V cores form the foundation of IQonIC Works silicon devices, enabling high performance, powerful integration, and application-specific configurability across a wide range of embedded systems.

While IQonIC Works’ primary focus is delivering finished microcontroller and ASIC products, selected processor cores and platform IP are also available under flexible licensing models for customer-specific silicon programs. This includes soft IP, hard IP, and pre-validated platform designs, depending on project requirements.

IQonIC Works RISC-V technology is developed with a strong focus on real silicon deployment. Our processor cores, interrupt controllers, timers, and platform IP are validated as part of complete SoC implementations and are supported by firmware, development tools, and reference designs suitable for production use.

Processor Cores and Platform Components

IQonIC Works develops a family of RISC-V processor cores and platform IP that are integrated into IQonIC Works silicon devices. These cores are designed to scale from small, low-power embedded applications to higher-performance systems requiring caches, memory protection, and advanced interrupt handling.

RISC-V Processor Cores Used in IQonIC Works Devices

The following RISC-V processor cores are used as building blocks within IQonIC Works microcontrollers and custom ASIC platforms. They are also available as standalone IP for customer-specific silicon programs where appropriate.

RISCV core progression

IQonIC Works RISC-V Cores come with a full suite of design IP including:

  • RISC-V IP (Core and Platform IP) package
  • Synthesizable RTL
  • Verification IP, Simulation test bench and basic test cases
  • Example synthesis scripts
  • Documentation
    • Data sheet, integration guide, programmer’s guide
  • Reference designs
    • FPGA project files and sample firmware source code

RV32IC_P5 Processor Core IP

IQonIC Works RV32IC_P5 Core is a larger, 5-stage pipeline core RISC-V processor, designed to meet the needs of medium-scale embedded applications that require higher performance, cache memories, and running a mix of trusted firmware and user application code.

RISC-V RV32IC_P5 CORE: BLOCK DIAGRAM
RISCV core block diagram

IQonIC Works RV32IC_P5 Core can be used in both ASIC- and FPGA-based design flows, and offers the following features:

  • RISC-V RV32I base instruction set, compliant with RISC-V User-Level ISA V2.2.
  • RISC-V “A” standard extension instructions for critical sections in a uniprocessor system.
  • RVC standard 16-bit compressed instructions for common RV32 instructions, for reduced code size.
  • Machine-mode and user-mode privileged architecture with direct physical addressing of memory, compliant with RISC-V Privileged Architecture Version 1.10.
  • Optional standard physical memory protection (PMP) with configurable number of entries, to support protected execution of application code.
  • Optional “N” standard extension for user-mode exception and interrupt handling.
  • Optional “M” standard extension for integer multiplication and division instructions.
  • Provision for application-specific instruction set extensions, e.g. for DSP operations.
  • 20 extended interrupts, plus timer and software interrupts.
  • Provision for external interrupt controller for additional interrupt sources.
  • All interrupts and exceptions, including those delegated to user mode, may be vectored for fast interrupt response.
  • Wait-for-interrupt instruction supports clock gating for low-power idle state.
  • 5-stage pipeline comprising fetch, decode, execute, memory access, and write back stages.
  • Optional branch prediction, branch target buffer, and return address stack, with configurable sizes and associativity, for reduced branch latency.
  • Tightly-coupled scratchpad memory interfaces for ASIC ROM and SRAM memories or FPGA block memories.
  • Optional instruction and write-back data cache memories with configurable line sizes, number of sets, and associativity.
  • AHB-Lite interfaces for extended memory and memory-mapped I/O.
  • GNU tool chain and Eclipse development environment for firmware development.
  • Accompanying machine-mode timers (AHB and APB versions) operating in processor clock domain or separate always-on timer clock domain.
  • Accompanying platform-level interrupt controller (PLIC) for up to 1023 interrupt sources and separate machine-mode and user-mode targets.

The processor core interfaces to separate compiled memory blocks for code and data memories, and to memory-mapped I/O blocks connected to AHB and APB buses. The application diagram shows that the processor AHB buses connect as masters to an AHB multilayer matrix, along with a DMA controller master. Slaves on the bus matrix include a RISC-V timer, a RISC-V PLIC, and a bridge to an APB bus for smaller I/O controllers.

RISC-V RV32IC_P5 CORE: APPLICATION DIAGRAM
RISC V Core Application Diagram

RV32EC_P2 Processor Core IP

 

IQonIC Works RV32EC_P2 Core is a 2-stage pipeline RISC-V processor core, designed to meet the needs of small, low-power embedded applications, running only trusted firmware.

The RV32EC_P2 processor core can be used in both ASIC- and FPGA-based design flows, and offers the following features:

  • RISC-V RV32E base instruction set, compliant with RISC-V User-Level ISA V2.2.
  • RVC standard 16-bit compressed instructions for common RV32 instructions, for reduced code size.
  • Optional “M” standard extension for integer multiplication and division instructions.
  • Optional inclusion of full RV32I register set (32 registers).
  • Provision for application-specific instruction set extensions, e.g. for DSP operations.
  • Simple machine-mode privileged architecture with direct physical addressing of memory, compliant with RISC-V Privileged Architecture Version 1.10.
  • 20 extended interrupts, plus timer and software interrupts.
  • Provision for external interrupt controller for additional interrupt sources.
  • All interrupts and exceptions vectored for fast interrupt response.
  • Wait-for-interrupt instruction supports clock gating for low-power idle state.
  • 2-stage pipeline comprising fetch and execute stages. Most instructions complete in one clock cycle.
  • Tightly-coupled memory interfaces for ASIC ROM and SRAM memories or FPGA block memories.
  • AHB-Lite or APB interface for extended memory and memory-mapped I/O.
  • GNU tool chain and Eclipse development environment for firmware development.
  • Accompanying machine-mode timers (AHB and APB versions) operating in processor clock domain or separate always-on timer clock domain.
  • Accompanying platform-level interrupt controller (PLIC) for up to 1023 interrupt sources.
Risc-v RV32EC_P2 Core

RISC-V RV32EC_P2 CORE

The processor interfaces to separate compiled memory blocks for code and data memories, and to memory mapped I/O blocks connected to Advanced High-Performance Bus (AHB) and Advanced Peripheral Bus (APB) buses. A clock control block gates clocks to the core depending on the operating mode.

RISC-V RV32EC_P2 CORE: APPLICATION WITH AHB INTERFACE
RISC V AHB Application Diagram

For simpler systems, a variant of the processor core provides just an APB interface for I/O devices. Other aspects are the same as for the variant with AHB interface.

RISC-V RV32EC_P2 CORE: APPLICATION WITH APB INTERFACE
RISC V with APB Interface

Platform Components Integrated in IQonIC Works SoCs

IQonIC Works microcontrollers integrate a set of RISC-V platform components that support real-time operation, scalable interrupt handling, and flexible system integration. These components are validated as part of complete SoC designs and are configurable to match application requirements.

RISC-V Timer IP

IQonIC Works RISC-V Timer IP comprises a suite of timers, each conforming to the RISC-V standard machine timer specification. For simple applications in which the timer counts processor-clock cycles, variants are provided without clock-domain crossing (CDC). Alternatively, for low-power applications in which the system clock may be gated-off or disabled, IQonIC Works also offers a variant with CDC counts of cycles of a low-frequency always-on clock (e.g., a clock provided by a low-power 32kHz oscillator). Variants of the timer with AHB bus interfaces allow for use in systems with complex bus structures. Alternatively, variants with APB bus interfaces allow for use in small systems with simple APB-only bus structures.

RISC-V TIMERS: APPLICATION DIAGRAM WITH AHB INTERFACE
RISC V TIMERS Application diagram with AHB interface
RISC-V TIMERS: APPLICATION DIAGRAM WITH APB INTERFACE
RISC-V TIMERS WITH APB Interface

Toolchain & Development Support

IQonIC Works provides a comprehensive development and prototyping environment to support firmware development, system integration, and customer-specific silicon programs. These tools are used internally to develop and validate IQonIC Works devices and can be made available to customers as part of development and customisation engagements.

IQonIC Works IP is backed by customisation and software development toolchain support, including RISC-V FPGA models and support for easy development and deployment within the VSCode and Eclipse IDEs.
 
  • Rapid Prototyping Toolchain for Custom ISA Extensions
    • Auto-generated assembler/disassembler
    • GDB server
  • Software development toolchain
    • Virtual Prototyping of RISC-V based SoCs and systems
    • RISC-V FPGA + Eclipse SW IDE System

IP Availability and Custom Silicon Programs

For customers using IQonIC Works devices or engaging in custom silicon development, IQonIC Works provides a comprehensive set of deliverables and optional supporting IP blocks to accelerate system integration and deployment.

Deliverables

  • Synthesizable Verilog RTL
  • Sample synthesis script for trial synthesis
  • Detailed data sheet and integration guide
  • Reference designs
  • Optional product/project support services

Related IP:

  • SPI master and SPI slave controllers
  • I2C master and I2C & I3C slave controllers
  • UART controller
  • General purpose I/O (GPIO) controller
  • Watchdog and sleep timers

For more information on IQonIC Works’ unique range of products and ASTC services supporting RISC-V product development, please contact us.

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